1. Field of the Invention
This invention relates to an intermediate potential generating circuit, formed in a semiconductor integrated circuit, which produces an intermediate potential from the power source voltage applied to the device.
2. Description of the Related Art
As the scale of semiconductor integrated circuit devices has become larger in recent years, intermediate potential generating circuits with large current driving capabilities but small power consumption have come to be required.
Thus, an intermediate potential generating circuit such as that shown in FIG. 1 has been conceived. This related art circuit is described in the Specification of Japanese Application (Showa) No. 60-125670.
The construction of the intermediate potential generating cirucit shown in FIG. 1 is as follows. First, two types of intermediate potential are generated by high resistance elements R1 and R2, N-channel type MOS trannsistor Q1 and P-channel type MOS transistor Q2. These two types of intermediate potential are respectively supplied to the gates of N-channel type MOS transistor Q3 and P-channel type MOS transistor Q4. Transistor Q3 and Q4 have large current drive capabilities and are connected in series between the power sources V.sub.DD and V.sub.SS. Then, an intermediate potential is obtained from the node between transistors Q3 and Q4.
Here, if the threshold voltages of N-channel type MOS transistors Q1 and Q3 are taken as V.sub.tn1 and V.sub.tn3 and the threshold voltages of P-channel type MOS transistors Q2 and Q4 are taken as V.sub.tp2 and V.sub.tp4, the relationship EQU V.sub.tn1 +.vertline.V.sub.tp2 .vertline.&lt;V.sub.tn3 +.vertline.V.sub.tp4 .vertline.
must be satisfied in order to prevent a through current flowing between power source V.sub.DD and ground power source V.sub.SS. However, it is difficult to achieve the above kind of threshold value relationship without increasing the complexity of the production processes.
In order to solve this problem, an intermediate potential generating circuit is described in the Specification of Japanese Patent Application (Showa) No. 61-65142. In this intermediate potential generating circuit, the back gate of N-channel type MOS transistor Q1 is connected to the node n3 between transistor Q1 and Q2. By doing this, since the threshold voltage of transistor Q1 is lowered by the substrate bias effect, it becomes possible to satisfy the threshold value relationship given without increasing the difficulty of the production processes. Moreover, in this FIG., the case of high resistance elements R1 and R2 being replaced by P-channel type MOS transistor Q5 and N-channel type MOS transistor Q6 is shown. In this arrangement, the channel lengths of transistors Q5 and Q6 are made longer than normal and their channel widths are made narrower than normal.
In this way, by using the configurations shown in FIGS. 1 and 2, intermediate potential generating circuits can be obtained with high current driving capability but low power consumption. However, their outputs, that is to say their intermediate potentials, are greatly influenced by the fluctuation of power source V.sub.DD, as shown in FIG. 3.
In FIG. 3, V.sub.n1 is the potential of node n1 to which the gate of transistor Q3 is connected, V.sub.n2 is the potential of node n2 to which the gate of transistor Q4 is connected, V.sub.n3 is the potential of node n3 between transistors Q1 and Q2, and V.sub.out is the potential of the node between transistors Q3 and Q4, that is to say the output potential.
As can be seen from this FIG., if power source V.sub.DD varies from 3[V] to 7[V], the output potential V.sub.out which is set at 1.5[V] when power source V.sub.DD is 3[V], varies from 1.5[V] according to the variation of power source V.sub.DD.
An intermediate potential is normally used as the plate voltage for memory cells constructed of capacitors in order to prevent insulation breakdown. However, in cases such as in FIG. 3 where the output of the intermediate potential generating circuit depends largely on the fluctuation of power source V.sub.DD, there are times when the cell data can be destroyed by this fluctuation. This is caused by the fact that when, for example, the potential of power source V.sub.DD is greatly reduced by noise or the like, the potential of the N-type diffusion layer which forms the memory node of the capacitor also reduces due to coupling, this in turn causes the PN junction between the N-type diffusion layer and the P-type diffusion layer to generate a forward bias.